The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
ICs are commonly formed by depositing a sequence of material layers, some of which are patterned by a lithography process. Double patterning techniques may be utilized to fabricate complex patterns. The double patterning techniques usually provide lower and upper photoresist layers disposed on a substrate. The materials in the lower and upper photoresist layers may intermix with each other, which will negatively impact the formation of the patterns. Furthermore, as the technology nodes shrink, the process overlay margins also shrink, and become more and more critical. Therefore, there is also a need to reduce the impact of overlay errors in the double patterning techniques. Moreover, the double patterning techniques usually involve multiple development or etch process steps, which are significant contributors to the overall cost of manufacturing, including processing time and the cost of materials. Accordingly, a method to address the above issues is needed.